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1/12 february 2003 STD100NH02L n-channel 24v - 0.0042 w - 60a dpak/ipak stripfet? iii power mosfet n typical r ds (on) = 0.0042 w @ 10 v n typical r ds (on) = 0.005 w @ 5 v n r ds(on) * qg industrys benchmark n conduction losses reduced n switching losses reduced n low threshold device n through-hole ipak (to-251) power package in tube (suffix -1") n surface-mounting dpak (to-252) power package in tape & reel (suffix t4") description the STD100NH02L utilizes the latest advanced design rules of sts proprietary stripfet? technology. this is suitable fot the most demanding dc-dc converter application where high efficiency is to be achieved. applications n specifically designed and optimised for high efficiency dc/dc convertes type v dss r ds(on) i d STD100NH02L 24 v < 0.0048 w 60 a (2) 3 2 1 1 3 ipak to-251 (suffix -1) dpak to-252 (suffix t4) absolute maximum ratings symbol parameter value unit v spike(1) drain-source voltage rating 30 v v ds drain-source voltage (v gs = 0) 24 v v dgr drain-gate voltage (r gs = 20 k w ) 24 v v gs gate- source voltage 20 v i d (2) drain current (continuous) at t c = 25c 60 a i d (2) drain current (continuous) at t c = 100c 60 a i dm (3) drain current (pulsed) 240 a p tot total dissipation at t c = 25c 100 w derating factor 0.67 w/c e as (4) single pulse avalanche energy 800 mj t stg storage temperature -55 to 175 c t j max. operating junction temperature internal schematic diagram
STD100NH02L 2/12 thermal data electrical characteristics (t case = 25 c unless otherwise specified) off on (5 ) dynamic rthj-case rthj-amb t l thermal resistance junction-case thermal resistance junction-ambient maximum lead temperature for soldering purpose max max 1.5 100 275 c/w c/w c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 25 ma, v gs = 0 24 v i dss zero gate voltage drain current (v gs = 0) v ds = 20 v v ds = 20 v t c = 125c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 20v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a 1 1.8 v r ds(on) static drain-source on resistance v gs = 10 v i d = 30 a v gs = 5 v i d = 15 a 0.0042 0.005 0.0048 0.009 w w symbol parameter test conditions min. typ. max. unit g fs (5) forward transconductance v ds = 10 v i d = 30 a 50 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 15v f = 1 mhz v gs = 0 3940 1020 110 pf pf pf r g gate input resistance f = 1 mhz gate dc bias = 0 test signal level = 20 mv open drain 1.1 w
3/12 STD100NH02L switching on switching off source drain diode (1) garanted when external rg=4.7 w and t f < t fmax . (5) pulsed: pulse duration = 300 s, duty cycle 1.5 %. ( 2 ) value limited by wire bonding (6) q oss = c oss * d v in , c oss = c gd + c ds . see appendix a (3) pulse width limited by safe operating area. (7) gate charge for synchronous operation ( 4 ) starting t j = 25 o c, i d = 30a, v dd = 15v . . symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 10 v i d = 30 a r g = 4.7 w v gs = 10 v (resistive load, figure 3) 15 200 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 10 v i d = 60 a v gs = 10 v 62 12 8 84 nc nc nc q oss (6) output charge v ds = 16 v v gs = 0 v 24 nc q gls (7) third-quadrant gate charge v ds < 0 v v gs = 10 v 56.5 nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 10 v i d = 30 a r g = 4.7 w, v gs = 10 v (resistive load, figure 3) 60 35 47 ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm (3) source-drain current source-drain current (pulsed) 60 240 a a v sd (5) forward on voltage i sd = 30 a v gs = 0 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 60 a di/dt = 100a/s v dd = 15 v t j = 150c (see test circuit, figure 5) 47 58 2.5 ns nc a electrical characteristics (continued) safe operating area thermal impedance
STD100NH02L 4/12 output characteristics transfer characteristics transconductance static drain-source on resistance gate charge vs gate-source voltage capacitance variations
5/12 STD100NH02L normalized gate threshold voltage vs temperature normalized on resistance vs temperature source-drain diode forward characteristics normalized breakdown voltage vs temperature . .
STD100NH02L 6/12 fig. 1: unclamped inductive load test circuit fig. 1: unclamped inductive load test circuit fig. 2: unclamped inductive waveform fig. 3: switching times test circuits for resistive load fig. 4: gate charge test circuit fig. 5: test circuit for inductive load switching and diode recovery times
7/12 STD100NH02L dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a3 0.7 1.3 0.027 0.051 b 0.64 0.9 0.025 0.031 b2 5.2 5.4 0.204 0.212 b3 0.85 0.033 b5 0.3 0.012 b6 0.95 0.037 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 15.9 16.3 0.626 0.641 l 9 9.4 0.354 0.370 l1 0.8 1.2 0.031 0.047 l2 0.8 1 0.031 0.039 a c2 c a3 h a1 d l l2 l1 1 3 = = b3 b b6 b2 e g = = = = b5 2 to-251 (ipak) mechanical data 0068771-e
STD100NH02L 8/12 dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a2 0.03 0.23 0.001 0.009 b 0.64 0.9 0.025 0.035 b2 5.2 5.4 0.204 0.212 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 9.35 10.1 0.368 0.397 l2 0.8 0.031 l4 0.6 1 0.023 0.039 == d l2 l4 1 3 == b e == b2 g 2 a c2 c h a1 detail "a" a2 detail "a" to-252 (dpak) mechanical data 0068772-b
9/12 STD100NH02L
STD100NH02L 10/12 sw1 sw2 appendix a buck converter: power losses estimation the power losses associated with the fets in a synchronous buck converter can be estimated using the equations shown in the table below. the formulas give a good approximation, for the sake of performan ce comparison, of how different pairs of devices affect the converter efficiency. however a very important parameter, the working temperature, is not considered. the real device behavior is really dependent on how the heat generated inside the devices is r emoved to allow for a safer working junction temperature. the low side ( sw2 ) device requires: very low r ds(on) to reduce conduction losses small q gls to reduce the gate charge losses small c oss to reduce losses due to output capacitance small q rr to reduce losses on sw 1 during its turn-on the c gd /c gs ratio lower than v th /v gg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; the high side ( sw1) device requires: small r g and l s to allow higher gate current peak an d to limit the voltage feedback on the gate small q g to have a faster commutation and to reduce gate charge losses low r ds(on) to reduce the conduction losses.
11/12 STD100NH02L high side switch (sw1) low side switch (sw2) conduction p d * i * r 2 l ds(on)sw1 ) 1 ( * i * r 2 l ds(on)sw2 d - switching p g l i i * f * ) q (q * v gd(sw1) gsth(sw1) in + zero voltage switching recovery not applicable 1 f * q * v rr(sw2) in diode p conduction not applicable f * t * i * v deadtime l f(sw2) ) gate(q g p f * v * q gg g(sw1) f * v * q gg gls(sw2) qoss p 2 f * q * v oss(sw1) in 2 f * q * v oss(sw2) in parameter meaning d duty- cycle q gsth post threshold gate charge q gls third quadrant gate charge pconduction on state losses pswitching on-off transition losses pdiode conduction and reverse recovery diode losses pgate gate drive losses qoss p output capacitance losses 1 dissipated by sw1 during turn-on
STD100NH02L 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 2002 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com

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